1. Field of the Invention
The present invention relates in general to digital circuits, and more particularly to high-speed data latching circuits for temporarily storing digital information.
2. Background of the Invention
Digital processing circuits often require latches for temporarily storing digital signals when transferring such signals between circuits. Such applications include high-speed A/D and D/A converters, high-speed memories such as RAMs, ROMs, and EEPROMs, high-speed pipelined logic circuits, and other applications.
U.S. Pat. No. 5,767,717 discloses a high-performance dynamic logic compatible and scannable transparent latch for dynamic logic. The dynamic logic compatible and scannable transparent latch consists of a switchable input inverter, an output inverter and a switchable feed back inverter. Additionally, the known dynamic logic compatible latch consists of a transmission circuit, which provides for selectively connecting data or scan data to the latch. The single clock signal is a square wave having a high-level and a low-level, preferably equal to the upper reference voltage and the lower reference voltage, respectively. During the period that the single clock signal is in one state, as in the low-level, the latch is operating in a latch phase. When operating in a second state, such as the high-level, the latch operates in an evaluate phase. The known dynamic compatible latch has taken advantage of dynamic logic to simplify the latch design. Particularly it is designed for high-speed reaction to a falling edge.
The known latch is not compatible for static logic and is not a scannable multiport latch, i.e. a latch consisting of at least three data inputs. This can be seen in that the signal level at the data inputs of the known latch needs to be a high-level signal but not a low-level signal, in order to store the data signal in the known dynamic logic latch.
It is an object of the present invention to provide a static logic compatible latch.
It is a further object of the present invention to provide a static logic compatible latch, which consists of multiple data inputs, i.e. a static logic compatible multiport latch.
It is another object of the present invention to provide a high performance static logic compatible multiport latch.
It is still another object of the present invention to provide a static logic compatible multiport latch, which is controlled by at least a first and a second clock.
It is yet another object of the present invention to provide a static logic multiport latch, which is operated by at least two clocks or clock signals and each being independent from the other clock signal.
It is another object of the present invention to provide a static logic compatible multiport latch, which consists of at least first data input ports and second data input ports.
It is a further object of the present invention to provide a static logic compatible multiport latch in which the data on the first data input ports are clocked faster through the static logic compatible multiport latch than data applied to the second data input ports.